ReP USP - Resultado da busca

Artigo de periodico
Application of fluorine based plasma etching processes in microfluidic device fabrication (2000)
Mansano, Ronaldo Domingues ; Verdonck, Patrick Bernard; Simões, Eliphas Wagner; Furlan, Rogério
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS ELETRÔNICOS
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ABNT
MANSANO, Ronaldo Domingues et al. Application of fluorine based plasma etching processes in microfluidic device fabrication. Journal of Solid-State Devices and Circuits, v. 8, n. 1, p. 5-9, 2000Tradução . . Acesso em: 27 abr. 2024.
APA
Mansano, R. D., Verdonck, P. B., Simões, E. W., & Furlan, R. (2000). Application of fluorine based plasma etching processes in microfluidic device fabrication. Journal of Solid-State Devices and Circuits, 8( 1), 5-9.
NLM
Mansano RD, Verdonck PB, Simões EW, Furlan R. Application of fluorine based plasma etching processes in microfluidic device fabrication. Journal of Solid-State Devices and Circuits. 2000 ; 8( 1): 5-9.[citado 2024 abr. 27 ]
Vancouver
Mansano RD, Verdonck PB, Simões EW, Furlan R. Application of fluorine based plasma etching processes in microfluidic device fabrication. Journal of Solid-State Devices and Circuits. 2000 ; 8( 1): 5-9.[citado 2024 abr. 27 ]
Artigo de periodico
Silicon surface roughness induced by SF6-based reactive ion etching process for micromachining applications (1998)
Verdonck, Patrick Bernard; Mansano, Ronaldo Domingues ; Maciel, Homero Santiago; Salvadori, Maria Cecília Barbosa da Silveira
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
VERDONCK, Patrick Bernard et al. Silicon surface roughness induced by SF6-based reactive ion etching process for micromachining applications. Journal of Solid-State Devices and Circuits, v. 6, n. 1, p. 1-6, 1998Tradução . . Acesso em: 27 abr. 2024.
APA
Verdonck, P. B., Mansano, R. D., Maciel, H. S., & Salvadori, M. C. B. da S. (1998). Silicon surface roughness induced by SF6-based reactive ion etching process for micromachining applications. Journal of Solid-State Devices and Circuits, 6( 1), 1-6.
NLM
Verdonck PB, Mansano RD, Maciel HS, Salvadori MCB da S. Silicon surface roughness induced by SF6-based reactive ion etching process for micromachining applications. Journal of Solid-State Devices and Circuits. 1998 ; 6( 1): 1-6.[citado 2024 abr. 27 ]
Vancouver
Verdonck PB, Mansano RD, Maciel HS, Salvadori MCB da S. Silicon surface roughness induced by SF6-based reactive ion etching process for micromachining applications. Journal of Solid-State Devices and Circuits. 1998 ; 6( 1): 1-6.[citado 2024 abr. 27 ]
Artigo de periodico
A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction (1997)
Nicolett, Aparecido Sirley; Martino, João Antonio
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
NICOLETT, Aparecido Sirley e MARTINO, João Antonio. A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction. Journal of Solid-State Devices and Circuits, v. 5, n. 1, p. 5-8, 1997Tradução . . Acesso em: 27 abr. 2024.
APA
Nicolett, A. S., & Martino, J. A. (1997). A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction. Journal of Solid-State Devices and Circuits, 5( 1), 5-8.
NLM
Nicolett AS, Martino JA. A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction. Journal of Solid-State Devices and Circuits. 1997 ;5( 1): 5-8.[citado 2024 abr. 27 ]
Vancouver
Nicolett AS, Martino JA. A simple technique to reduce the influence of the series resistance on the BULK and SOI MOSFET parameter extraction. Journal of Solid-State Devices and Circuits. 1997 ;5( 1): 5-8.[citado 2024 abr. 27 ]
Artigo de periodico
E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications (1997)
Soares Junior, João Navarro ; Van Noije, Wilhelmus Adrianus Maria
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
SOARES JUNIOR, João Navarro e VAN NOIJE, Wilhelmus Adrianus Maria. E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications. Journal of Solid-State Devices and Circuits, v. 5, n. 2, p. 21-26, 1997Tradução . . Acesso em: 27 abr. 2024.
APA
Soares Junior, J. N., & Van Noije, W. A. M. (1997). E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications. Journal of Solid-State Devices and Circuits, 5( 2), 21-26.
NLM
Soares Junior JN, Van Noije WAM. E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications. Journal of Solid-State Devices and Circuits. 1997 ; 5( 2): 21-26.[citado 2024 abr. 27 ]
Vancouver
Soares Junior JN, Van Noije WAM. E-TSPC: extended true single-phase-clock MOS circuit technique for high speed applications. Journal of Solid-State Devices and Circuits. 1997 ; 5( 2): 21-26.[citado 2024 abr. 27 ]
Artigo de periodico
Improved channel lenght and series resistance extraction for short-channel MOSFETs suffering from mobility degradation (1997)
Nicolett, Aparecido Sirley; Martino, João Antonio ; Simoen, Eddy ; Claeys, Cor
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
NICOLETT, Aparecido Sirley et al. Improved channel lenght and series resistance extraction for short-channel MOSFETs suffering from mobility degradation. Journal of Solid-State Devices and Circuits, v. 5, n. 1, p. 1-4, 1997Tradução . . Acesso em: 27 abr. 2024.
APA
Nicolett, A. S., Martino, J. A., Simoen, E., & Claeys, C. (1997). Improved channel lenght and series resistance extraction for short-channel MOSFETs suffering from mobility degradation. Journal of Solid-State Devices and Circuits, 5( 1), 1-4.
NLM
Nicolett AS, Martino JA, Simoen E, Claeys C. Improved channel lenght and series resistance extraction for short-channel MOSFETs suffering from mobility degradation. Journal of Solid-State Devices and Circuits. 1997 ; 5( 1): 1-4.[citado 2024 abr. 27 ]
Vancouver
Nicolett AS, Martino JA, Simoen E, Claeys C. Improved channel lenght and series resistance extraction for short-channel MOSFETs suffering from mobility degradation. Journal of Solid-State Devices and Circuits. 1997 ; 5( 1): 1-4.[citado 2024 abr. 27 ]
Artigo de periodico
Quantitative analysis of an enhanced diffusion along interfacial misfit dislocations in 'SI' / 'SI' ('GE') heterostructures (1996)
Braga, Nelson Liebentritt de Almeida; Zasnicoff, Luiz Sergio
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
BRAGA, Nelson Liebentritt de Almeida e ZASNICOFF, Luiz Sergio. Quantitative analysis of an enhanced diffusion along interfacial misfit dislocations in 'SI' / 'SI' ('GE') heterostructures. Journal of Solid-State Devices and Circuits, v. 4 , n. ja 1996, p. 1-6, 1996Tradução . . Acesso em: 27 abr. 2024.
APA
Braga, N. L. de A., & Zasnicoff, L. S. (1996). Quantitative analysis of an enhanced diffusion along interfacial misfit dislocations in 'SI' / 'SI' ('GE') heterostructures. Journal of Solid-State Devices and Circuits, 4 ( ja 1996), 1-6.
NLM
Braga NL de A, Zasnicoff LS. Quantitative analysis of an enhanced diffusion along interfacial misfit dislocations in 'SI' / 'SI' ('GE') heterostructures. Journal of Solid-State Devices and Circuits. 1996 ;4 ( ja 1996): 1-6.[citado 2024 abr. 27 ]
Vancouver
Braga NL de A, Zasnicoff LS. Quantitative analysis of an enhanced diffusion along interfacial misfit dislocations in 'SI' / 'SI' ('GE') heterostructures. Journal of Solid-State Devices and Circuits. 1996 ;4 ( ja 1996): 1-6.[citado 2024 abr. 27 ]
Artigo de periodico
New empirical model for leakage drain current of soi mosfets valid from room to high temperatures (1996)
Bellodi, Marcello; Martino, João Antonio ; Flandre, Denis
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
BELLODI, Marcello e MARTINO, João Antonio e FLANDRE, Denis. New empirical model for leakage drain current of soi mosfets valid from room to high temperatures. Journal of Solid-State Devices and Circuits, v. 4 , n. ja 1996, p. 7-10, 1996Tradução . . Acesso em: 27 abr. 2024.
APA
Bellodi, M., Martino, J. A., & Flandre, D. (1996). New empirical model for leakage drain current of soi mosfets valid from room to high temperatures. Journal of Solid-State Devices and Circuits, 4 ( ja 1996), 7-10.
NLM
Bellodi M, Martino JA, Flandre D. New empirical model for leakage drain current of soi mosfets valid from room to high temperatures. Journal of Solid-State Devices and Circuits. 1996 ;4 ( ja 1996): 7-10.[citado 2024 abr. 27 ]
Vancouver
Bellodi M, Martino JA, Flandre D. New empirical model for leakage drain current of soi mosfets valid from room to high temperatures. Journal of Solid-State Devices and Circuits. 1996 ;4 ( ja 1996): 7-10.[citado 2024 abr. 27 ]
Artigo de periodico
2.488 gb / s 1: 4/1:16 demultiplexer : an experience on the design of high-speed digital 'GA''AS' ics (1996)
Correra, Fatima Salete ; Abrao, T
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
CORRERA, Fatima Salete e ABRAO, T. 2.488 gb / s 1: 4/1:16 demultiplexer : an experience on the design of high-speed digital 'GA''AS' ics. Journal of Solid-State Devices and Circuits, v. 4 , n. ja 1996, p. 24-31, 1996Tradução . . Acesso em: 27 abr. 2024.
APA
Correra, F. S., & Abrao, T. (1996). 2.488 gb / s 1: 4/1:16 demultiplexer : an experience on the design of high-speed digital 'GA''AS' ics. Journal of Solid-State Devices and Circuits, 4 ( ja 1996), 24-31.
NLM
Correra FS, Abrao T. 2.488 gb / s 1: 4/1:16 demultiplexer : an experience on the design of high-speed digital 'GA''AS' ics. Journal of Solid-State Devices and Circuits. 1996 ;4 ( ja 1996): 24-31.[citado 2024 abr. 27 ]
Vancouver
Correra FS, Abrao T. 2.488 gb / s 1: 4/1:16 demultiplexer : an experience on the design of high-speed digital 'GA''AS' ics. Journal of Solid-State Devices and Circuits. 1996 ;4 ( ja 1996): 24-31.[citado 2024 abr. 27 ]
Artigo de periodico
Achievement of high quality thin gates oxides grown by rapid thermal oxidation of silicon (1995)
Santos Filho, Sebastião Gomes dos ; Hasenack, Claus Martin
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
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ABNT
SANTOS FILHO, Sebastião Gomes dos e HASENACK, Claus Martin. Achievement of high quality thin gates oxides grown by rapid thermal oxidation of silicon. Journal of Solid-State Devices and Circuits, v. 3 , n. 1 , p. 1-9, 1995Tradução . . Acesso em: 27 abr. 2024.
APA
Santos Filho, S. G. dos, & Hasenack, C. M. (1995). Achievement of high quality thin gates oxides grown by rapid thermal oxidation of silicon. Journal of Solid-State Devices and Circuits, 3 ( 1 ), 1-9.
NLM
Santos Filho SG dos, Hasenack CM. Achievement of high quality thin gates oxides grown by rapid thermal oxidation of silicon. Journal of Solid-State Devices and Circuits. 1995 ;3 ( 1 ): 1-9.[citado 2024 abr. 27 ]
Vancouver
Santos Filho SG dos, Hasenack CM. Achievement of high quality thin gates oxides grown by rapid thermal oxidation of silicon. Journal of Solid-State Devices and Circuits. 1995 ;3 ( 1 ): 1-9.[citado 2024 abr. 27 ]
Artigo de periodico
Linear time algorithm for transistor chaining of static and dynamic cmos circuits with applications to sog structures (1995)
Romão, Fábio Luís; Van Noije, Wilhelmus Adrianus Maria
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
ROMÃO, Fábio Luís e VAN NOIJE, Wilhelmus Adrianus Maria. Linear time algorithm for transistor chaining of static and dynamic cmos circuits with applications to sog structures. Journal of Solid-State Devices and Circuits, v. 3 , n. 1 , p. 30-4, 1995Tradução . . Acesso em: 27 abr. 2024.
APA
Romão, F. L., & Van Noije, W. A. M. (1995). Linear time algorithm for transistor chaining of static and dynamic cmos circuits with applications to sog structures. Journal of Solid-State Devices and Circuits, 3 ( 1 ), 30-4.
NLM
Romão FL, Van Noije WAM. Linear time algorithm for transistor chaining of static and dynamic cmos circuits with applications to sog structures. Journal of Solid-State Devices and Circuits. 1995 ;3 ( 1 ): 30-4.[citado 2024 abr. 27 ]
Vancouver
Romão FL, Van Noije WAM. Linear time algorithm for transistor chaining of static and dynamic cmos circuits with applications to sog structures. Journal of Solid-State Devices and Circuits. 1995 ;3 ( 1 ): 30-4.[citado 2024 abr. 27 ]
Artigo de periodico
Near-exact two-dimensional mathematical model for pipe diffusion along dislocations (1995)
Braga, Nelson Liebentritt de Almeida
Source: Journal of Solid-State Devices and Circuits. Unidade: EP
Assunto: CIRCUITOS INTEGRADOS
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
BRAGA, Nelson Liebentritt de Almeida. Near-exact two-dimensional mathematical model for pipe diffusion along dislocations. Journal of Solid-State Devices and Circuits, v. 3 , n. 1 , p. 10-3, 1995Tradução . . Acesso em: 27 abr. 2024.
APA
Braga, N. L. de A. (1995). Near-exact two-dimensional mathematical model for pipe diffusion along dislocations. Journal of Solid-State Devices and Circuits, 3 ( 1 ), 10-3.
NLM
Braga NL de A. Near-exact two-dimensional mathematical model for pipe diffusion along dislocations. Journal of Solid-State Devices and Circuits. 1995 ;3 ( 1 ): 10-3.[citado 2024 abr. 27 ]
Vancouver
Braga NL de A. Near-exact two-dimensional mathematical model for pipe diffusion along dislocations. Journal of Solid-State Devices and Circuits. 1995 ;3 ( 1 ): 10-3.[citado 2024 abr. 27 ]

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